SRAM is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM (DRAM) which must be periodically refreshed. An SRAM cell has three different states: standby, read and write. The SRAM to operate in read mode and write mode should have “readability” and “write stability” respectively.
When not accessed, the bitlines are precharged to a predetermined state. Precharging to supply voltage can cause cell disturbance (cell stability issue) when the WL is turned ON for access, precharging to a very low value can make it difficult to write to the cell. An optimum value needs to be chosen that works best for stability and Writeability, across process corners. A lower-than-supply voltage precharge value also helps improve the performance. In the read access state, the reading process requires only asserting the wordline WL and reading the SRAM cell state by a single access transistor and bit line. Nevertheless bitlines are relatively long with large parasitic capacitance. Therefore to speed-up reading, more complex processes are used in practice; that is, driving the bit lines to a threshold voltage (midrange voltage between logical 1 and 0).
By asserting the word line WL, both the access transistors are enabled which cause that the bitline voltage to either slightly drop or rise. Then the two bitlines will have a small voltage difference between them while reaching a sense amplifier, which will sense which line has the higher voltage thus determining whether there was “1” stored or “0” stored. The higher the sensitivity of the sense amplifier, the faster the speed of the read operation.